With the transmitter keyed, the 100 Watt Transceiver output is connected though the T/R relay on the VSWR/XFMR PWB Assy to the RF input, A1J1-9, of the Tube PWB Assy. A1C1 is a DC blocking capacitor that prevents the cathode bias voltage from being fed back to the transceiver's output. Capacitor A1C2 and inductor A1L2 are a high frequency L-C matching network. The cathode bias voltage from the Power Control PWB Assy enters the Tube PWB Assy through connector A1J1-4/5 and is rf filtered by capacitor A1C3 and inductor A1L1. If the normal cathode bias circuit should fail open, resistor A1R1 at the cathode of V1 would develop a cutoff bias for V1. For a complete discussion of the bias circuit see paragraph 5-12-f for the Power Control PWB Assy. The cathode of the amplifier tube, V1, is indirectly heated by an isolated filament whose power, 5 Vac, is derived from the secondary of filament transformer T1. The primary voltage, 115 Vac, of T1 enters the tube Assembly through A1J1-12 and A1J1-14.

b. Plate circuits. The DC plate voltage enters the Tube PWB Assy through a high voltage connector, P1, and is filtered by plate choke L1 and bypass capacitor C5. The rf output of tube, V1, passes through the output coupling/DC blocking capacitor C4 to the output connector. The DC plate voltage is sampled and divided down to a level usable by both the Power Control PWB Assy and the Micro control PWB Assy by resistors R1 and A1R2. Zener diode A1VR2 provides protection and capacitor A1C4 acts as an rf bypass.

c. RF Plate Sample Circuit. The rf plate sample circuit provides an output that is proportional to the rf voltage present at the plate of the tube. This output is used by the Micro Control PWB Assy for tuning of the Tank Assy and is compared with a DC plate voltage sample as part of the power control and protection circuitry on the Power Control PWB Assy.

The RF plate sample circuit is made up of a capacitor divider, a peak detector, and a resistor divider. The capacitor divider is formed by capacitors C2 and C3. Diode CR1, inductor L2, and capacitor C7 form the peak detector. Resistors A1R3, A1R4, and A1R5 divide the output of the peak detector to a level that is usable by the Micro Control PWB Assy. One volt of output at A1J1-3 represents 1000 volts of peak rf voltage swing at the plate of the tube. VR1 prevents the output at J1-3 from going above a level that is usable by the Micro Control PWB Assy.

5-9. TANK ASSEMBLY A2.

Tank Assembly A2 includes all of the reactive tuning and loading components and their related control systems. Schematic coverage for this assembly ls on two separate schematic (in the depot manual). The overall assembly schematic includes all detail except the Servo/Bandswitch Drive Assembly. A separate schematic details the Servo/Bandswitch Drive Assembly only.

a. RF Circuits. The Tank Assembly uses a pi network to transform the output impedance, nominally 50 ohms, to a higher impedance at the plate of the amplifier tube, nominally 1600 ohms. The pi network is composed of bandswitched tune capacitors, Tune Cap PWB Assemblies A1 and A2, variable inductor L1, fixed inductors on coil PWB Assembly A5, bandswitched load capacitors, and Load Cap PWB Assemblies A3 and A4. Both the Tune CAP PWB Assemblies and the Load Cap PWB Assemblies are made up of groups of fixed capacitors that are added together by a three-pole bandswitch. As an example, the tune capacitors for bard 1 are capacitors A1C1, A1C2, A1C3_ A1C4. A1C5, and A1C6, while the tune capacitor for bard 2 are A1C3, A1C4, A1C5, A1C6, A1C7, and A1C8. Likewise, the Load Cap PWB Assy follows in a similar manner. The fixed inductors on the Coil PWB Assembly are switched in and out by bandswitch S1C (refer to figure 5-4). Bandswitch S1 (S1A, S1B, and S1C) is driven by motor B1 whose control is from the Servo/Bandswitch Drive PWB Assy and open seeking switch wafer S2. The variable coil L1 is the only tuning element in the Tank Assy, and its control is through the Coil Drive Assy and the Servo/Bandswitch Drive PWB Assy.

b. Bandswitch Drive Circuit. The Servo/Bandswitch Drive Assembly PWB Assy A2A7 is the control interface for all units that make up the Tank Assembly A2. All control is from the Micro Control PWB Assy A6. Bandswitch control from A6 is a BCD code which is inverted to a decimal code by BCD-to-decimal decoder A7U1. The output of U1 presents a high, 5 volts, on one of the ten output lines indicating the band that is selected. The ten outputs are connected to the bandswitch decoding wafer, S2, through steering diodes A7CR5 through A7CR14 and RF filters A7R43 through A7R46 and A7C16 through A7C25. The decoding wafer is open seeking; that is, when a new band is selected, the output of the decoder U1 for that band goes high. That output is connected through its steering diode and rf filter to switch S2, through S2 and its common, S2-C, back to the Servo/Bandswitch Drive PWB Assy. The high from S2-C turns on bandswitch driver A7Q10 and A7Q11, energizing the bandswitch motor B1 through connector A7J3-1/2 and A7J3-3/4. The bandswitch motor runs until the decoding wafer's common opens at the band selected, removing the high from the bandswitch drive transistors and the drive to the motor. Resistors A7R21 and A7R22 divide the output motor voltage, 13.5 volts, down to 5 volts for a signal to the Micro Control PWB Assy to indicate that power is being supplied to the bandswitch motor. The Micro Control PWB Assy then generates an RF Mute signal to remove rf drive from the 100 Watt transceiver to prevent hot switching of the bandswitches.

c. Coil Drive Control Circuits. All in-band tuning is accomplished by the Coil Drive Assy A6 and Servo/Bandswitch Drive PWB Assy A7.

The Coil Drive Assy, A6, contains the coll drive motor, A6B1, and a limit switch, A6S1, which indicates when the variable coil is at either minimum or maximum inductance. Also, the A6 assembly has a shaft encoder, G1, that rotates turn for turn with the variable inductor. The outputs of the encoder, TWA and TWB, are pulses that are representative of the degree of rotation of the variable inductor. The two signals are shifted in phase such that the direction of rotation can be determined by sampling and comparing the two outputs.

The Servo/Bandswitch Drive PWB Assy, A7, contains the coil drive circuit. Since the circuit for driving the variable inductor toward minimum inductance is identical to that which drives the inductor toward maximum inductance, only one of the circuits will be discussed.

Control for driving the inductor toward minimum inductance enters the A7 assembly through J1-15. MIN L DRIVE, a low level signal, biases transistor Q4 on, which in turn biases both Q5 and Q6 on. With Q5 on, 13.5 volts is present at connector J2-5/6; and with Q6 on, ground is present at connector J2-7/8. This places 13.5 volt across the motor, such that it rotates the inductor toward minimum inductance. The MIN L DRIVE signal also biases Q7 on through resistor R13, which places 13.5 volts at the base of Q1. This inhibits Q1 from turning on, preventing the MAX L drive circuit from being active.

When no drive signal (either MIN L DRIVE or MAX L DRIVE) from the Micro Control PWB Assembly is present at the A7 Assembly, the coil drive motor A6B1 ls dynamically braked. Q9 is biased on through resistor R15. This biases both Q3 and Q6 on, which in turn places a ground at both J2-5/6 and J2-7/8 and across the motor. When either the MIN L DRIVE or MAX L DRIVE signal is present, Q9 is biased off through either CR2 or CR1, respectively, biasing both Q3 and Q6 off.

Limit switch information, either MIN L STOP or MAX L STOP, enters the A7 Assembly at J2-16 and J2-14. These signals are a high level, 13.5 volts. When the MIN L STOP is active, indicating that the variable inductor is at minimum inductance, transistor Q4 ls biased off through CR16, thus inhibiting the MIN L drive circuit and shutting off the drive to the motor. Also, Q14 is biased on, applying a ground to J1-5, which indicates to the Micro Control PWB Assembly that the inductor is at minimum inductance. The Micro Control Assembly then removes the MIN L DRIVE signal.

The 5 volt regulator circuit supplies 5 volts for the encoder A6G1 and the BCD-to-decimal decoder A7U1. This circuit is made up of pass transistor Q12, zener diode VR1, and bias resistor R24. Resistor R23 drops part of the voltage, reducing the power dissipation in Q12; and capacitors C13 and C14 filter the output.

5-10. VSWR/XFMR PWB ASSEMBLY A3.

Refer to the VSWR/XFMR schematic diagram for the following discussion This schematic is found in the depot Manual.

The VSWR/XFMR PWR Assembly contains an RF IN sample, a T/R relay, a VSWR bridge, an rf sample of the output power, and a transformer circuit that is used to aid in matching the output impedance of the Tank Assembly to the antenna load impedance.

The RF IN sample contains a capacitor divider of the RF input, a peak detector, and a resistor divider network. Capacitors C11 and C12 form the divider sampling the RF input from the 100 Watt Transceiver. Inductor L6, diode CR4, and capacitor C13 make up the peak detector. Resistors R12 and R13 divide the output of the peak detector to a level usable by the Micro Control PWB Assembly for sampling and display.

T/R relay K1 switches the RF input from the 100 Watt Transceiver from the antenna when in receive to the Tube Assembly when in transmit.

The VSWR bridge is designed to provide analog outputs for both the forward and the reflected power output components. Current transformers T2 and T3 and resistors R2 and R3 produce a voltage that is proportional to the current on the RF output line. Capacitors C1 and C2 provide a voltage divider on the RF output line. The above two voltages are vectorily added to produce two voltages. One voltage is proportional to the forward power and one is proportional to the reflected power. Resistors R4 and R5 and capacitor C4 provide an adjustment to balance the bridge into a purely 50 ohm resistive output impedance. Diode CR1 rectifies the reflected sample, while diode CR2 rectifies the forward sample. Resistor divider R6 and R7 provides a calibrated output for the reflected power sample. This sample is nominally adjusted for 7 volts output for 1000 watts reflected. Likewise, resistor divider R8 and R9 provides a calibrated output for the forward power, which is also set for 7 volts at 1000 watts forward output.

An rf monitor is picked off the rf output line between the VSWR bridge and the output connector P2. Resistors R10 and R11 comprise a voltage divider whose output is capable of being connected to standard test equipment.

The impedance transformer T1 is used to better match the antenna impedance to that of the Tank Assembly. The transformer has three taps, one that equates to an antenna impedance of 36 ohms, one at 50 ohms, and one at 81 ohms. The Micro Control PWB Assembly monitors the forward power sample and the rf plate voltage sample during the tune cycle. When the ratio of the rf plate voltage to the forward power is below a specified value, the Micro Control PWB Assembly actives the LOW Z input (an active low). When the ratio is within the specified window, the NOM Z input is activated. And when the ratio is higher than a specified value, the HIGH Z input is activated.

When the NOM Z input is selected, the active low biases on transistor Q2, which applies a positive 13.5 volts to the NOM Z relay K2. Relay K2 closes, connecting the output of the Tank Assembly directly to the antenna output connector P2.

When the LOW Z input is selected, the active low signal biases on Q1, which applies a positive 13.5 volts to the LOW Z relay K3. The rf output of the Tank Assembly is connected through transformer T1 and relay K3 to the antenna output connector P2. Transformer T1 and relay K3 to the antenna output connector P2. Transformer 71 has a 7:6 turns ratio, which equates to an impedance transformation of 49:36 ohms, thus optimizing the tank impedance for an antenna impedance of 36 ohms.

When the HIGH Z input is selected, transistor Q3 is biased on, activating HIGH Z relay K1. The rf output d the Tank Assembly is connected through transformer T1 with a 7:9 turns ratio. This equates to an impedance transformation of 50:81 ohms, thus optimizing the Tank Assembly's output impedance for matching to an antenna impedance of 81 ohms.

Only one of these inputs is active and then only when the LPA is in the transmitting mode. When in receive, all inputs are inactive, disconnecting the Tank Assembly from the antenna.

5-11. FAN INVERTER PWB ASSEMBLY A4.

The schematic for the Fan Inverter Assembly is located in the Depot Manual. The assembly contains a fan inverter circuit that converts the 13.5 Vdc to 115 Vac at 400 Hz.

The fan inverter circuit contains both a driver transformer, T1, which sets the frequency of oscillation and an output transformer, T2, which sets the output voltage. The 13.5 volt output of the regulator circuit is applied to the center tap of the output transformer and to the center tap of the driver transformer through a filter network, capacitors C1 and C2 and inductor L1, and a bias network, C3, GR1, R1, R2, and R3, which supplies the return path for the driver transistors, Q1 and Q2. Resistor R4 provides an offset voltage across T1 such that transistor Q2 is biased on more than Q1 when power is first applied. This starts the inverter oscillating.

As Q2 conducts, a voltage is induced in winding T2- 5/6 with a polarity that makes terminal 5 more positive than terminal 6. Then, by transformer action, terminal 1 is more positive than terminal 2. A voltage is also induced in driver transformer T1's primary that makes terminal T1-5 more positive than T1-1. By transformer action, secondary winding terminal T1-10 is more positive than terminal T1-8, causing Q2 to be more strongly forward biased. This action continues until Q2 is driven into saturation. When this occurs, the primary voltage can no longer increase and a condition of quasi-stable equilibrium is maintained. With a constant voltage across the windings, both the current and the magnetic flux increase until the core reaches saturation. At this time, the exciting current required by the transformer exceeds that which can be supplied by the Q2, causing Q2 to turn off. As the flux in the transformer collapses, the polarity in the transformer is opposite to that originally induced. Therefore, Q1 is biased on and is driven to saturation in a like manner. The flux will then again collapse, turning off Q1 and turning on Q2, thus completing the cycle. R-C networks R5/C4 and R6/C5 provide snubbing action to protect the transistors from any spikes that might be generated.

The AC voltage induced in the primary of T2 is coupled by transformer action to the secondary and to the output pins of J2. Capacitor C6 provides a phase shift for the fan.

5-12. POWER CONTROL PWB ASSEMBLY A5.

The Power Control PWB Assembly performs the following functions: meter processing, TGC and PPC generation, cathode biasing, and temperature sensor processing, Figure FO-2 is a simplified diagram of the power Control PWB Assembly. The Power Control PWB Assembly schematic is located in the Depot Manual.

a. Meter Processing Circuits. The forward and reflected power samples from the VSWR/XFMR PWB Assembly A3 are directed to the Power Control PWB Assembly for processing for both metering information for the LPA front panel and for power control processing for generation of the TGC and PPC control signals.

The forward power sample enters the power Control PWB Assembly at J2-8. Resistor network R5 and R9 sets the appropria1e bias level for the forward power sample from the output filter. Operational amplifier U1A has a gain of one and acts as a buffer to prohibit any interaction between the VSWR bridge on the VSWR/XFMR Assembly and the processing of the signal on the Power Control PWB Assembly. Diode CR1, resistors R15, and capacitor c5 peak detect the forward power sample, while divider network R17 and R19 sets the full power voltage to 4 volts at the input to FWD METERING AMP U2A. Amplifier U2A also has a gain of one and supplies the forward metering sample to the Micro Control PWB Assembly through J1-9 and to the 100 Watt Transceiver through J1-17. Zener diode VR4 inhibits the output from going above 5.1 volts.

The reflected power sample enters the Power control PWB Assembly at J2-7. Resistor network R6 and R27 sets the appropriate bias level for the reflected power sample from the VSWR/XFMR PWB Assembly. Operational amplifier U1B has a gain of three and acts as a buffer to prohibit any interaction between the VSWR bridge on the VSWR/XFMR PWB Assembly and the processing of the signal on the Power Control PWB Assembly. Diode CR2, resistor R16, and capacitor C6 peak detect the reflected power sample, while divider network R18 and R20 sets the full power reflected voltage to 4 volts at the input to REFLD METERING AMP U2B. Amplifier U2B also has a gain of one and supplies the forward metering sample to the Micro Control PWB Assembly through J1-6 and to the 100 Watt Transceiver through J1-18. Zener diode VR5 inhibits the output from going above 5.1 volts.

b. TCG Circuits. The TGC signal is generated from a combination of the forward power and reflected power samples. FWD/REFLD AMP U3A uses the higher of the two signals to generate the TGC signal. The reflected power sample becomes equal to the forward power sample when the output VSWR is 2:1. At VSWRs above 2:1, the reflected power sample will be the dominant sample and thus control the level of the TGC voltage. The gain of U3A is adjustable from 1 to 1.25 and is set to amplify the input voltage to 8 volts as well as compensate for any variation of the IF sample in the 100 Watt Transceiver. The output of U3B is fed to the Control Loop Variable Gain Amp consisting of U9A and U8.

Unijunction transistor U8 acts as a voltage variable resistor which modifies the gain of amplifier U9A. As the voltage at U8-3 goes negative, the gain of U9A is increased, causing the envelope of the forward and/or reflected power sample to increase. This increase is detected by the l 100 Watt Transceiver's TGC circuits as an rf power output signal increase, causing the rf power drive level to be reduced. There are four inputs that can cause a gain change if any of their thresholds are exceeded. The four inputs are the CW/FSK power threshold, the Ik cathode sample, the over temperature threshold, and the RF/DC plate sample.

The TGC output of amplifier U9A is connected through solid state switch U10 to output amplifier TGC Amp U9B. Switch U10 controls which signal is used as the TGC signal to the transceiver. When the LPA is in the tune mode, switch U10 is open, causing the power control of the LPA to be generated by the cathode current sample; and when in the ready mode, U10 is closed, enabling the control through the above path. LED DS1 indicates that there is TGC voltage being sent to the 100 Watt Transceiver, and diode CR26 prevents the TGC signal from going negative.

c. CW/FSK Power Control. This control is not normally used in the 1 KW LPA, but its operation if used is described below.

The forward/reflected power envelope is sampled through diode CR5 from the output of the FWD/REFLD Amp in the TGC control circuit by an averaging network consisting of diode CR6, capacitor C10, and resistors R32 and R33. Resistor R34 provides an adjustment of the output of this network to the input of the CW/FSK Avg Pwr Amp, U4A, which has a gain of two. The output of U4A is diode or-ed with the cathode sample, the ambient temperature sample, and the RF/DC plate sample to the Gain Control Threshold Amp U4B. When any of these samples exceed the threshold of 5 volts set by resistor divider R42 and R43, the output of U4B goes positive. The output of U4B is inverted by Gain Control Polarity Inverter U7A and fed to the controlling input of the unijunction transistor U8, thus increasing the gain of the Control Loop Gain Amp U9A and thereby causing the output power of the LPA to be decreased.

d. PPC Control Circuit. The PPC control circuit samples the outputs from the RF/DC plate comparator, the cathode current amplifier, and the FWD/REFLD Amp U3A. The cathode current sample and the forward/reflected power sample are divided by resistor network R107 and R108 and diode ORed to the output of the RF/DC plate comparator and inputted to the PPC Unit Gain Amp U5B. Amplifier U5B has unity gain and acts as a buffer amplifier to supply a PPC voltage to the 100 Watt Transceiver where it is thresholded at 5 volts. When the output of the PPC amplifier exceeds this level, the transceiver's PPC circuits cause the transceiver's RF output to drop to minimum output, thus causing an immediate power cutback out of the LPA. This circuit is used only as protection in the event that the TGC does not or cannot react to an overload to prevent damage to the LPA. The output of the PPC amplifier is also fed to the PPC Indicator Threshold Amp U13B. When the PPC output voltage exceeds 5 volts as set by resistor divider R116 and R117, the output of U13B goes high, lighting LED DS2, which indicates that the control loop is under PPC control.

e. RF/DC Plate Voltage Comparator. The peak RF voltage swing at the plate of the amplifier tube A1V1 is compared to the DC plate voltage. If the rf voltage swing approaches the maximum available swing as set by the DC plate voltage, a voltage is generated by the RF/OC Comparator and fed to both the TGC circuit and the PPC circuit for power cutback. This prevents the RF plate voltage swing from equaling the DC plate voltage and thus will prevent excessive grid current from being drawn by the amplifier tube.

The RF plate sample enters the power Control PWB Assembly on connector J1-36 and is fed to the Micro Control PWB Assembly through J1-10 for monitoring and display. Likewise, the DC plate sample enters the Power Control PWB Assembly through J1-1 and is fed to the Micro Control PWB Assembly through J1-8. Zener diode VR7 and resistor network R83, R84, and R85 set both the threshold level and the gain of the RF/DC Comparator U3B. When the threshold is exceeded (this varies directly with the DC plate voltage), the output of U3B goes high and is fed to both the TGC through diode CR29 and the PPC circuit through CR18. The rate at which the rf plate voltage approaches the DC plate voltage will determine whether the TGC loop or the PPC loop will control the output power.

f. Cathode Current and Bias Circuits. The Power Control PWB Assembly contains both the cathode bias circuit and the cathode current control and metering circuits.

The cathode bias is set by the B+ sample voltage, resistors R93 and R94, and transistors Q1, Q2, and Q3. When Q1 is biased off, the amplifier tube is biased off at approximately 20 volts. This voltage is set by a resistor divider network in the 1000 Watt Power Supply, resistor R93 and R94, and transistors Q2 and Q3. An active low KEYLINE signal present at J1-3 is inverted by Keyline Schmitt Trigger U11A to a high, which biases on Q1 and shots out R94, lowering the voltage at the base of Q2 to about 5 volts, thus biasing on Q2, Q3, and A1V1. The B+ sample also contains an AC component that is representative of the AC ripple on the DC plate supply. This affects the bias point in such a way that the AC hum component on the RF output signal is canceled or reduced.

Resistor R95 in the emitter lead of Q3 measures the cathode current. The resultant voltage is divided by resistor R96 and R98 and amplified by amplifier U5A. Resistor R96 is used to adjust the maximum plate current allowable before TGC/PPC cutback will take place. The gain of U5A is changed from approximately 31 during normal operation to approximately 120 during a tune cycle by the Tune Ik Switch being biased on by resistor R106 when Control Logic Switch U10 is open.

The LPA tunes on constant cathode current, and this is controlled by the output of U5A being fed to the input of the TGC Amp U9B through resistor R62 and diode CR16. During the TUNE mode, switch U10 is open, removing the forward/reflected power signal from the input to the TGC Amp and releasing the ground from diode CR15, allowing CR16 to conduct. During normal operation, switch U10 is closed, connecting the forward/reflected signal to the TGC Amp and grounding CR15, which reverse biases CR16 and biases off Tune Ik Switch Q4 through CR14.

The output of the cathode current amplifier is connected to the Gain Control Threshold Dmp U4B through diode CR10, resistor divider R47 and R48, and diode CR8. If the output of the amplifier exceeds 7.4 volts, then the threshold of the Gain Control Threshold Amp causes the gain of the TGC loop to increase, thus reducing the RF power output. In addition, the output of the Ik amplifier U5A is connected to the PPC Amp U5B through CR19 to generate a PPC signal if the cathode current should exceed approximately 800 milliamperes.

g. Control Logic Switch. Control Logic Switch U10, in addition to switching the TGC input from the forward/reflected sample in normal to the cathode current sample in tune, also removes the internal power control potentiometer from the circuit in tune mode and antenna tuna mode. Also, U10 switches the coupler tune power potentiometer into the TGC circuit when the antenna tune mode is selected (an active low signal). Both the Power Control potentiometer and the Coupler Tune Power potentiometer feed voltages to the input of the TGC Gain Control Polarity Inverter, which increases/decreases the gain of the TGC loop, thereby reducing/increasing the RF output power of the LPA.

h. Temperature Sensor Circuits. The Power Control PWB Assembly contains the processing circuits for the Temperature Sensor PWB Assembly outputs. There are two outputs for the temperature sensor: an output that is proportional to the ambient temperature and one that is proportional to the airflow past the sensor assembly.

The ambient sensor input at J2-3 is directed to two comparators, one for air flow and one for overtemperature. The output of the sensor is 10 millivolts per degree Kelvin, which correlates to 2.73 volts for 0 degrees Centigrade. The Over Temp Threshold Amp U6B compares the output of the ambient sensor to the threshold voltage equating to 150 degrees C, above which its output goes positive. The output of the amplifier is directed to the variable gain stage of the TGC loop through diode CR11, resistor R49 and R47, and diode CR8, thus causing cutback of the output power when this threshold is exceeded. It the ambient temperature is not reduced through power cutback but increases, this increased level is detected by Fault Inverter U11E. The output of the inverter goes low, indicating a XMTR FAULT and causing the LPA to go in standby. Feedback resistor R152 sets up a hysteresis loop in the Over Temp Threshold Amp so that once cutback has occurred, the temperature must decrease beyond a certain point before the LPA can be brought back to full output power.

The ambient sensor output is also compared to the heated sensor input by Air Flow Comparator U6A. When the heated sensor is between 15 and 21 degrees above the ambient sensor, the output of the Air Flow Comparator goes positive, such that the Air Flow Fault Threshold Amp U7B is enabled. The positive output of U7B goes positive lighting LED DS4, LO AIR, and causing the output of Fault Inverter U11E to go low, indicating a XMTR FAULT.

i. -8 Volt Regulator. The -8 volt regulator consists of an oscillator, an amplifier, a rectifier, and a filter. Schmitt Trigger Oscillator U11C, resistor R129, and capacitor C51 form an oscillator whose frequency is approximately 12 kHz. Power Amp U12 amplifies the output of U11C to 13.5 volts. Capacitor C54 couples the output of U12 to rectifiers CR24 and CR25 and filter C55. The output voltage is approximately -8 volts.

5-13. MICRO CONTROL PWB ASSEMBLY A6.

The Micro Control PWB Assembly controls all functions within the LPA except for Power Enable, which is a hardwired signal from the 100 Watt Transceiver used to turn on the LPA, and TGC/PPC control signals that are hardwired and under control of the Power Control PWB Assembly. Refer to the Micro Control PWB schematic for the following discussion. This schematic is found in the Depot Manual.

a. Transceiver Data Link. Data between the 100 Watt Transceiver and the LPA is serialized and transmitted via a two wire link. Opto isolator U4 isolates the link from the receive data input of microprocessor U1. The TXD output of microprocessor U1 is normally high when in the receive mode. This output biases transistor Q2 on through hex buffer U10-4/5, which enables the opto isolator's input for reception of data from the 100 Watt Transceiver. The receive data from U4-1 is inverted by NAND gate U3-5/6/4 and inputted to the RXD input of the microprocessor. The transmit data is from the TXD output of the microprocessor and is transmitted to the 100 Watt Transceiver via hex buffer U10-4/5, transistor Q2, and opto isolator U4.

b. Clock Circuits. The clock control signals for the Micro Control PWB Assembly are generated by the clock oscillator circuit. This circuit consists of crystal oscillator Y1, capacitor C38 and C39, resistor R1 and R2, and hex inverters U8-1/2, U8-3/4, and U8-5/6. The output frequency of this circuit is 4.9152 MHz. This signal is connected to both the XTAL1 input of microprocessor U1 and a dual 4-bit counter, U31, from which all other clock frequencies are derived.

Three outputs of counter U31 are used. The 614.4 kHz clock is used for the clock for the analog to digital converter U6. The 307.2 kHz clock output is inputted to counter U32 where it is further divided down to a 150 Hz clock. This is connected to the second 4-bit counter of U31 where it is divided down to produce a 9.373 Hz clock. This clock is inverted by hex inverter U17-1/2 and ANDed with the power on reset circuit of resistor R20 and capacitor C13 by NAND gale U3-1/2/3. The output of U3 is connected to the reset line of microprocessor U1. This both holds the microprocessor reset until the power supply stabilizes during power on and resets the micro if U31 is not reset within the clock frequency (approximately every .1 seconds) by the P3.4 output of U1 going low.

Counter U32, in addition to the 150 Hz clock, has three other clock outputs: a 153.6 kHz clock, a 300 Hz clock, and a 75 Hz clock. The first two are used by microprocessor U1, while the 75 Hz clock is used by the Front Panel PWB Assembly as the clock for the data display by the LCD.

c. Interrupts. The microprocessor has two interrupts: one is the 300 Hz clock, and the other is generated from the inputs of the Tank Assembly coll drive encoder, TWA and TWB. The TWA signal is shaped by Schmitt trigger inverter U17-9/8 and fed to an edge detector circuit, capacitors C36 and C37, resistors R5-8 and R5-10, and hex inverter U17-5/6. This circuit detects both a positive going and a negative going pulse. Likewise, the TWB signal is shaped by U17-11/10 and fed to an edge detector circuit, capacitors C24 and C29, resistors R5-6 and R5-7, and hex inverter U17-3/4. These four outputs, TWA positive going, TWA negative going, TWB positive going, and TWB negative going, are ORed and inverted by NOR gate U26. The output of U26 is fed to the second interrupt of microprocessor U1. When any motion of the coil drive assembly is detected, the microprocessor is interrupted and records the motion of the variable inductor, thus keeping track of its position.

d. Input Latch. The input latch U28 converts eight parallel inputs to a BYTE word that is read into the microprocessor as required. Five of these inputs are from the Tank Assembly: BD SW ON indicates bandswitch motion, TWA and TWB indicate direction and rotation of the variable inductor, and MIN L LIMIT and MAX L LIMIT indicate when the variable inductor is at either end stop. The EXT INTLK input is not used. The XMTR FAULT is from the power Control PWB Assembly and indicates a temperature fault. LPA KEY is a hardwired signal from the 100 Watt Transceiver, and when low activates the keylines in the LPA. The microprocessor polls the input latch as required by software by enabling the output enable input (OE) of U28.

e. Analog to Digital Converter. A/D Converter U6 converts any one of the eight inputs to a digital BYTE that is representative of the analog signal. All inputs are based on a 5 volt maximum value, while the output is an 8 Bit word. Microprocessor U1 selects which input is to be converted through address inputs A0, A1, A2, and address enable input ALE of U6. The START input of U6 starts the conversion process, while the OE input enables the output lines so that the microprocessor can read the BYTE word.

f. Microprocessor Circuits. The microprocessor U1 is an 8 bit control oriented CPU. It contains a 128 byte read/write data memory, a full duplex UART, two 16 bit timer/counters, a programmable I/O, a 64 K byte bus expansion control, and oscillator and clock circuits. It can address up to 64 K bytes of external program memory and/or 64 bytes of external data.

The external program memory is contained in EPROM U2, while the data is held both in the on-chip memory as well as in the external RAM U29.

lnput/output ports P0.0 through P0.7 serve as both address data outputs as well as data inputs. I/O ports P2.0 through P2.7 serve only as output address ports. Latch U12 latches the output address data, while the I/O ports are accepting data. Address decoder U27 decodes the address and the read and write commands for control of the external RAM U29, the Input Latch U28, the A/D Converter U6, and the Output Latch U13. Parallel to serial converter U15 converts up to eight parallel inputs to a serial eight bit word. The 1000 Watt LPA identification bit (KW ID) ls the only input to U15.

I/O ports P1.0 through P1.7 are used for control and data to/from the Front Panel Assembly. Data is sent to and received from the Front Panel Assembly in serial form through the serial data line. Serial Clk is the clock signal for clocking in/out data to/from the shift registers on the Front Panel Assembly, LCD OUT ENABLE enables the LCD display, while F.P. IN ENABLE enables the front panel switch data to be sent to the microprocessor. F.P. OUT ENABLE enables the front panel LEDs.

g. Output Latches. Serial data from the microprocessor is clocked into 2 serial to parallel output latches U19 and U25 for control of the LPA. Output drivers U20 and U30 are open collector Darlington transistor arrays that act as buffers between the output device and the serial to parallel latches. One output RF MUTE is sent to the 100 Watt Transceiver as a hardwired input for shutting off the RF drive form the transceiver during certain LPA operations.

Output Latch U13 is a parallel in/parallel out latch for latching parallel data from the microprocessor to the output. These outputs are also buffered by an open collector Darlington transistor array and serve as control for the Tank Assembly.

There are a number of hardwired jumpers on the Micro Control PWB Assembly that program the method of control of the keylines. Both the T/R KEYLINE and the KEYLINE are programmed to be under microprocessor U1 control according to the inputs from either the 100 Watt Transceiver in AUTO mode or the front panel in MANUAL mode.

5-14. FRONT PANEL ASSEMBLY A7.

The Front Panel Assembly contains both display and manual controls for operation of the LPA. Display is from both a group of LEDs and from an LCD whose input is controlled by a rotary switch. There are four toggle switches, one pushbutton switch, and two rotary switches.

a. LED Display. Information for four of the five LEDs is sent to the Front Panel Assembly via the serial data line from the Micro Control PWB Assembly. The serial data is clocked into the serial to parallel convener U26 by the F.P. OUT EN signal from the Micro Control PWB Assembly. The data is converted to parallel data by U26, and the parallel outputs of U26 drive their respective LED transistor drivers and LEDs.

The fifth LED, POWER ENABLE, is controlled by the 5 volt supply from the Micro Control PWB Assembly to indicate that power is present in the LPA.

b. LCD Display. The LCD display DS1 is a 4 digit, 8 segment display that is driven by LCD driver U28. The information for display is serially clocked into the driver chip U28 by the LCD CLK line and the LCD OUT EN line from the Micro Control PWB Assembly.

c. Manual control switches. Manual control switches, TUNE PWR, LOCAL KEY, TUNE, and ANTENNA, as well as the SELF TEST pushbutton switch, are inputted to parallel in serial out chip U20. When the microprocessor activates the FP IN EN line along with the SERIAL CK, the data from the switches is sent to the microprocessor on the Micro Control PWB Assembly.

d. Rotary Switches. Data from the two rotary switches, METER and AUTO MANUAL BAND, is inputted to parallel in serial out chips U17, U18, and U19. These converters are controlled via the FP IN EN and SERIAL CK lines from the Micro Control PWB Assembly. It should be noted that the serial data from all front panel switches with the exception of the POWER ENABLE switch are linked together through parallel to serial converters U17, U18, U19, and U20.

5-15. TEMPERATURE SENSOR PWB ASSEMBLY A8.

Refer to the power Control PWB Assembly schematic for the following discussion. This schematic is found in the Depot Manual.

The Temperature Sensor PWB Assembly contains two temperature sensitive integrated circuits, U1 and U2. The output of the ICs varies directly with their temperature. For every degree Kelvin, the output increases 10 millivolts, such that at a room ambient of 20 degrees centigrade, the output would be 2.93 volts. Both outputs are fed to the Power Control PWB Assembly for processing.

a. Heated Sensor Circuit. The Heated Sensor U1 is preheated by resistor R1 to raise its temperature above the ambient temperature. If there is sufficient air flow past this sensor, it will be held at a lower temperature than if there was no air flow but still at a higher temperature than the ambient. This temperature is typically 7 degrees. Thus, the output of U1 will be representative of the air flowing past the sensor assembly.

b. Ambient Sensor Circuit. Ambient Sensor U2 measures the ambient temperature. It also contains an adjustment R2 to calibrate k with the U1 heated sensor. Resistor R3 acts to equate the thermal mass of U1 to that of U2.

5-16. INTERCONNECT PWB ASSEMBLY A9.

Refer to the Interconnect PWB Assembly schematic for the following discussion. This schematic is found in the Depot Manual.

The Interconnect PWB Assembly serves as a distribution board for the low voltage DC supply from the 1000 Watt Power Supply and also contains the H.V. ON driver and the primary power sample circuits.

Resistor divider R1 and R2 sample the low voltage power supply as an indication of the primary power input.

The active low H.V. ON signal from the Micro Control PWB Assembly that controls the high voltage contactor in the 1000 Watt Power Supply enters the Interconnect PWB Assembly on connector J1-2. This signal when low biases on transistor Q1, which in turn biases on Q2, providing a low signal on J3-2 if interlock switch S1 is closed. Diode CR2 clamps the contactor's coil when turned on.

5-17. LOW PASS FILTER ASSEM8LY A10.

Refer to the VSWR/XFMR Schematic diagram for the following discussion. This schematic is found in the Depot Manual.

The Low pass Filter Assembly is a three section filter designed to attenuate any signal, whether harmonic or spurious related, above 30 MHz. It is in both the transmit and the receive path.